The present invention generally relates to electrical circuits and, more specifically, to circuits for an analog-to-digital converter and methods of operating an analog-to-digital converter.
A successive approximation register (SAR) analog-to-digital converter (ADC) commonly employs a capacitive digital-to analog converter (CDAC) in which the constituent capacitors are switched between a reference voltage and ground to set an appropriate output voltage. Although an ideal CDAC outputs a reference voltage that is precisely linear, real-world CDACs are subject to influence by external factors, such as temperature, and are therefore susceptible to errors. For example, as temperature varies, the reference voltage output by the CDAC may drift and, accordingly, a gain error may be introduced.
A Time-Interleaved ADC may include a time-multiplexed parallel array of n identical successive approximation register (SAR) slices that increase the net sample rate, even though each individual slice in the array is actually sampling at a lower rate. Each SAR slice includes a buffer, such as a source follower, that has one or more transistors that provide a voltage drop relative to a stable reference voltage presented to its input. However, the output voltage may exhibit a significant temperature variation among the different SAR slices due to, for example, process variations among the transistors in the different SAR slices. The result is a temperature dependence that may cause different SAR slices to output different voltages despite receiving the same reference voltage.
Currently, the voltages of the different slices cannot be separately adjusted and calibrated. Such separate adjustments are desirable to provide a mechanism for compensating gain differences due to fabrication-related mismatches. Moreover, the separate adjustments should be enabled without adding to the temperature variations.
Accordingly, improved circuits for an analog-to-digital converter and methods of operating an analog-to-digital converter are needed.